Supported Memories And Transactions; Table 106. Multiplexed I/O Nor Flash; Table 107. Nonmultiplexed I/Os Psram/Sram - ST STM32F101 series Reference Manual

RM0008
NOR Flash, multiplexed I/Os
FSMC signal name
CLK
A[25:16]
AD[15:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT
NOR-Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit
(26 address lines).
PSRAM/SRAM
FSMC signal name
CLK
A[25:0]
D[15:0]
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1]
NBL[0]
PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
21.5.2

Supported memories and transactions

Table 108
transactions when the memory data bus is 16-bit for NOR, PSRAM and SRAM.
Transactions not allowed (or not supported) by the FSMC in this example appear in gray.

Table 106. Multiplexed I/O NOR Flash

I/O
O Clock (for synchronous access)
O Address bus
I/O 16-bit multiplexed, bidirectional address/data bus
O Chip select, x = 1..4
O Output enable
O Write enable
Latch enable (this signal is called address valid, NADV, by some NOR
O
Flash devices)
I NOR Flash wait input signal to the FSMC

Table 107. Nonmultiplexed I/Os PSRAM/SRAM

I/O
O Clock (only for PSRAM synchronous access)
O Address bus
I/O Data bidirectional bus
O Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
O Output enable
O Write enable
O Address valid only for PSRAM input (memory signal name: NADV)
I PSRAM wait input signal to the FSMC
O Upper byte enable (memory signal name: NUB)
O Lowed byte enable (memory signal name: NLB)
below displays an example of the supported devices, access modes and
DocID13902 Rev 15
Flexible static memory controller (FSMC)
Function
Function
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