Clock-Out Capability; Rcc Registers; Clock Control Register (Rcc_Cr) - ST STM32F101 series Reference Manual

RM0008
8.2.10

Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One of 8 clock signals can be selected as the MCO
clock.
•
SYSCLK
•
HSI
•
HSE
•
PLL clock divided by 2 selected
•
PLL2 clock selected
•
PLL3 clock divided by 2 selected
•
XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
•
PLL3 clock selected (for Ethernet)
The selected clock to output onto MCO must not exceed 50 MHz (the maximum I/O speed).
The selection is controlled by the MCO[3:0] bits of the
(RCC_CFGR).
8.3

RCC registers

Refer to
8.3.1

Clock control register (RCC_CR)

Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
31 30 29 28
PLL3 PLL3
RDY ON
Reserved
r rw
15 14 13 12
r r r
Bits 31:30
Bit 29 PLL3RDY: PLL3 clock ready flag
Bit 28 PLL3ON: PLL3 enable
Section 2.1 on page 47
27 26 25
PLL2 PLL2
PLLRD
RDY ON
Y
r rw r
11 10 9
HSICAL[7:0]
r r r r
Reserved, must be kept at reset value.
Set by hardware to indicate that the PLL3 is locked.
0: PLL3 unlocked
1: PLL3 locked
Set and cleared by software to enable PLL3.
Cleared by hardware when entering Stop or Standby mode.
0: PLL3 OFF
1: PLL3 ON
Connectivity line devices: reset and clock control (RCC)
for a list of abbreviations used in register descriptions.
24 23 22
PLLON
Reserved
rw
8 7 6
HSITRIM[4:0]
r rw rw
DocID13902 Rev 15
Clock configuration register
21 20 19 18
HSEBY
CSSON
P
rw rw
5 4 3 2
Res.
rw rw rw
17 16
HSERDY HSEON
r rw
1 0
HSIRDY HSION
r rw
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