Adc Control Register 2 (Adc_Cr2) - ST STM32F101 series Reference Manual

Analog-to-digital converter (ADC)
Bit 6 AWDIE: Analog watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Bit 5 EOCIE: Interrupt enable for EOC
This bit is set and cleared by software to enable/disable the End of Conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits
These bits are set and cleared by software. They select the input channel to be guarded by
the Analog watchdog.
00000: ADC analog Channel0
00001: ADC analog Channel1
....
01111: ADC analog Channel15
10000: ADC analog Channel16
10001: ADC analog Channel17
Other values reserved.
Note: ADC1 analog Channel16 and Channel17 are internally connected to the temperature
11.12.3

ADC control register 2 (ADC_CR2)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
JEXTT
JEXTSEL[2:0]
RIG
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239/1128
sensor and to V
REFINT
ADC2 analog inputs Channel16 and Channel17 are internally connected to V
ADC3 analog inputs Channel9, Channel14, Channel15, Channel16 and Channel17 are
connected to V .
SS
27 26 25
Reserved
11 10 9
ALIGN Reserved
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DocID13902 Rev 15
, respectively.
24 23 22
TSVRE SWSTA JSWST
FE RT ART
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8 7 6
DMA
Reserved
rw
21 20 19 18
EXTTR
EXTSEL[2:0]
IG
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5 4 3 2
RST
CAL
CAL
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RM0008
.
SS
17 16
Res.
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1 0
CONT ADON
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