Interrupt Vector Table; Interrupt Control Register (Icr00-63); Hold Request Cancel Level Register (Hrcl); Table 2-7: Interrupt Control Register - Fujitsu F2MC-FR Series Application Note

2.5.2 Table Base Register (TBR)
The TBR contains the start address of the vector table to be used during EIT processing. Its
initial value after reset is 0x000FFC00.
It is possible to relocate the interrupt vector table to the required address during run time by
configuring the TBR accordingly. Both the mode and reset vector have a fixed addresses
0x000FFFF8 and 0x000FFFFC respectively. These addresses remains fix, although the
TBR register is rewritten because its initial value after reset is 0x000FFC00.
It should be noted that the TBR register should not be assigned values greater than
0xFFFFFC00.

2.5.2.1 Interrupt Vector Table

The Interrupt Vector Table is a set of 256 words, which contains the 32-bit starting address
of corresponding Interrupt Service Routines.
The vector address is calculated is as follows:
Vector address = TBR + Offset value = TBR + 0x03FC - 4 x Vector number
First 16 interrupts vectors are for special purpose EITs where as the later vectors are for
peripheral interrupts. For more information please refer the hardware manual.

2.5.3 Interrupt Control Register (ICR00-63)

Using these registers interrupt levels of peripheral interrupts can be configured.
Bit Bit
No. Name
7-5 -
4 ICR4
3-0 ICR3-0
It should be noted that there is single such register for two peripherals, hence the interrupt
level for such two peripherals are SAME. For example ICR00 configures the same interrupt
level for External Interrupt 0 as well as External Interrupt 1. If a value of 31 is written to such
register then the corresponding peripheral interrupt is disabled.

2.5.4 Hold Request Cancel Level Register (HRCL)

The DMA controller can request the CPU for the D-Bus by asserting D-Bus hold request
(DHREQ), the CPU in turn would respond to this DMA request by D-Bus hold acknowledge
(DHACK) granting the access of the D-Bus to the DMA.
In such situation NMI or peripheral interrupt can cancel the hold request (depending upon
configuration of LVL bits if HRCL register) and gain the access of the bus while
corresponding ISR executes. Upon execution of RETI instruction the DMA would gain
access to the D-Bus again (provided the MHALTI flag and the corresponding peripheral
interrupt flag is cleared in the ISR).
© Fujitsu Microelectronics Europe GmbH
INTERRUPTS
Chapter 2 Interrupt Types
Initial
Description
Value
- -
This bit is read-only and the write to this bit is ignored. Since the
power-on reset value of this bit is 1, if the value of 0x0F is
1
attempted to be written to ICR register then the actual ICR value
would become 0x10.
These bits along with ICR4 configure the interrupt level of the
1111
corresponding peripheral.

Table 2-7: Interrupt Control Register

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