Altera cyclone V Technical Reference page 2549

Hard processor system

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USB 2.0 OTG Controller

Send Feedback

This bit is valid only for IN Endpoints This interrupt

is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or

completely empty status is determined by the TxFIFO

Empty Level bit in the Core AHB Configuration

Applies to periodic IN endpoints only. This bit can be

cleared when the application clears the IN endpoint

NAK by writing to DIEPCTLn.CNAK. This interrupt

indicates that the core has sampled the NAK bit Set

(either by the application or by the core). The

interrupt indicates that the IN endpoint NAK bit Set

by the application has taken effect in the core.This

interrupt does not guarantee that a NAK handshake is

sent on the USB. A STALL bit takes priority over a

Applies to non-periodic IN endpoints only. Indicates

that the data in the top of the non-periodic TxFIFO

belongs to an endpoint other than the one for which

the IN token was received. This interrupt is asserted

on the endpoint for which the IN token was received.

No interrupt

Transmit FIFO Empty interrupt

No interrupt

IN Endpoint NAK Effective interrupt

No interrupt

IN Token Received with EP Mismatch

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