Altera cyclone V Technical Reference page 2291

Hard processor system

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This register reflects the mask for Channel 4 interrupt status bits.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

USB 2.0 OTG Controller

Send Feedback

In non Scatter/Gather DMA mode, it indicates the

transfer completed abnormally either because of any

USB transaction error or in response to disable

request by the application or because of a completed

transfer. In Scatter/gather DMA mode, this indicates

that transfer completed due to any of the following .

EOL being set in descriptor . AHB error . Excessive

transaction errors . Babble . Stall

Transfer completed normally without any errors. This

bit can be set only by the core and the application

should write 1 to clear it.

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

Channel not halted

Channel Halted

Transfer completed normally without any

Base Address

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