Altera cyclone V Technical Reference page 2166

18-76
grxstsr
Bit
6
ginnakeffmsk
4
rxflvlmsk
3
sofmsk
2
otgintmsk
1
modemismsk
grxstsr
A read to the Receive Status Read and Pop register additionally pops the: top data entry out of the RxFIFO.
The receive status contents must be interpreted differently in Host and Device modes. The core ignores the
receive status pop/read when the receive FIFO is empty and returns a value of 0. The application must only
pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register
(GINTSTS.RxFLvl) is asserted. Use of these fields vary based on whether the HS OTG core is functioning
as a host or a device. Do not read this register's reset value before configuring the core because the read
value is "X" in the simulation.
Altera Corporation
Name
Mode: Device only.
Value
0x0
0x1
Mode: Host and Device.
Value
0x0
0x1
Mode: Host and Device.
Value
0x0
0x1
Mode: Host and Device.
Value
0x0
0x1
Mode: Host and Device.
Value
0x0
0x1
Description
Description
Global Non-periodic IN NAK Effective Mask
No mask Global Non-periodic IN NAK
Effective
Description
Receive FIFO Non-Empty Mask
No maks Receive FIFO Non-Empty
Description
Start of Frame Mask
No Mask Start of Frame
Description
OTG Interrupt Mask
No mask OTG Interrupt
Description
Mode Mismatch Interrupt Mask
No Mask Mode Mismatch Interrupt
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
USB 2.0 OTG Controller
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