Altera cyclone V Technical Reference page 2225

Hard processor system

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USB 2.0 OTG Controller

Send Feedback

The application writes a nonzero value to this field to

put the port into a Test mode, and the corresponding

pattern is signaled on the port.

The application uses this field to control power to this

port, and the core can clear this bit on an over current

Indicates the current logic level USB data lines. Bit

[10]: Logic level of D+ Bit [11]: Logic level of D-

When the application sets this bit, a reset sequence is

started on this port. The application must time the

reset period and clear this bit after the reset sequence

is complete. The application must leave this bit Set for

at least a minimum duration mentioned below to

start a reset on the port. The application can leave it

Set for another 10 ms in addition to the required

minimum duration, before clearing the bit, even

though there is no maximum limit set by theUSB

standard. This bit is cleared by the core even if there is

no device connected to the Host. High speed: 50 ms

Full speed/Low speed: 10 ms

Test mode disabled

Test_SE0_NAK mode

Test_Packet mode

Test_force_Enable

Logic level of D+

Logic level of D-

Port not in reset

Port in reset

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