Altera cyclone V Technical Reference page 2138

Hard processor system

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hstnegsucstschng

sesreqsucstschng

This register can be used to configure the core after power-on or a change in mode. This register mainly

contains AHB system-related configuration parameters. Do not change this register after the initial

programming. The application must program this register before starting any transactions on either the

AHB or the USB.

Module Instance

Altera Corporation

Mode: Host and Device. The core sets this bit on the

success or failure of a USB host negotiation request.

The application must read the Host Negotiation

Success bit of the OTG Control and Status register

(GOTGCTL.HstNegScs) to check for success or

failure. This bit can be set only by the core and the

application should write 1 to clear it.

Mode: Host and Device. The core sets this bit on the

success or failure of a session request. The application

must read the Session Request Success bit in the OTG

Control and Status register (GOTGCTL.SesReqScs) to

check for success or failure. This bit can be set only by

the core and the application should write 1 to clear it.

Mode:Host and Device.This bit can be set only by the

core and the application should write 1 to clear it.

Host Negotiation Status Change

Session Request Status

Non Active State

Set when utmisrp_bvalid signal is deasserted

Base Address

USB 2.0 OTG Controller

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