Altera cyclone V Technical Reference page 2459

cv_5v4
2016.10.28
dieptsiz12
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
diepdma12
DMA Addressing.
dtxfsts12
on page 18-589
This register contains the free space information for the Device IN endpoint TxFIFO.
diepdmab12
DMA Buffer Address.
diepctl13 on page 18-591
Endpoint_number: 13
diepint13
on page 18-597
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
dieptsiz13
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
diepdma13
DMA Addressing.
dtxfsts13
on page 18-603
This register contains the free space information for the Device IN endpoint TxFIFO.
diepdmab13
DMA Buffer Address.
diepctl14
on page 18-605
Endpoint_number: 14
diepint14
on page 18-611
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
USB 2.0 OTG Controller
Send Feedback
on page 18-587
on page 18-588
on page 18-590
on page 18-601
on page 18-602
on page 18-604
Device Mode Registers Register Descriptions
18-369
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