Altera cyclone V Technical Reference page 2460

18-370
Device Mode Registers Register Descriptions
dieptsiz14
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
diepdma14
DMA Addressing.
dtxfsts14
on page 18-617
This register contains the free space information for the Device IN endpoint TxFIFO.
diepdmab14
DMA Buffer Address.
diepctl15
Endpoint_number: 15
diepint15
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
dieptsiz15
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
diepdma15
DMA Addressing.
dtxfsts15
on page 18-631
This register contains the free space information for the Device IN endpoint TxFIFO.
diepdmab15
DMA Buffer Address.
doepctl0 on page 18-633
This is Control OUT Endpoint 0 Control register.
doepint0
on page 18-636
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
Altera Corporation
on page 18-615
on page 18-616
on page 18-618
on page 18-619
on page 18-625
on page 18-629
on page 18-630
on page 18-632
cv_5v4
2016.10.28
USB 2.0 OTG Controller
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