Altera cyclone V Technical Reference page 2493

cv_5v4
2016.10.28
Bit
3
inepmsk3
2
inepmsk2
1
inepmsk1
0
inepmsk0
dvbusdis
This register specifies the VBUS discharge time after VBUS pulsing during SRP.
Module Instance
usb0
usb1
Offset:
0x828
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
USB 2.0 OTG Controller
Send Feedback
Name
Value
0x1
0x0
Value
0x1
0x0
Value
0x1
0x0
Value
0x1
0x0
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
No Interrupt mask
IN Endpoint 3 Interrupt mask
Description
No Interrupt mask
IN Endpoint 2 Interrupt mask
Description
No Interrupt mask
IN Endpoint 1 Interrupt mask
Description
No Interrupt mask
IN Endpoint 0 Interrupt mask
Base Address
0xFFB00828
0xFFB40828
18-403
dvbusdis
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Register Address
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