Altera cyclone V Technical Reference page 2142

18-52
gusbcfg
Bit
0
glblintrmsk
gusbcfg
This register can be used to configure the core after power-on or a changing to Host mode or Device
mode. It contains USB and USB-PHY related configuration parameters. The application must program
this register before starting any transactions on either the AHB or the USB. Do not make changes to this
register after the initial programming.
Module Instance
usb0
usb1
Offset:
0xC
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30 29
corru force force
pttxp devmo hstmo
kt de de
WO RW RW
0x0 0x0 0x0
15 14 13
Reserved
Altera Corporation
Name
Mode: Host and device. The application uses this bit
to mask or unmask the interrupt line assertion to
itself. Irrespective of this bits setting, the interrupt
status registers are updated by the core.
Value
0x0
0x1
Base Address
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
28 27 26 25
txend Reserved ulpi
delay
RW
RW 0x0
0x0
12 11 10 9
usbtrdtim hnpca
p
RW 0x5
RW
0x0
Description
Description
Mask the interrupt assertion to the applica‐
tion
Unmask the interrupt assertion to the
application.
0xFFB0000C
0xFFB4000C
Bit Fields
24 23 22
indic compl terms ulpie
ator ement eldlp xtvbu
ulse sindi
RW RW
cator
0x0 0x0 RW
0x0
8 7 6
srpca ddrse physe fsint
p l l
RW RW RO
0x0 0x0 0x0
Register Address
21 20 19 18
ulpie ulpic ulpia
xtvbu lksus utore
sdrv m s
RW RW RW
RW 0x0 0x0 0x0
0x0
5 4 3 2
ulpi_ phyif
f utmi_
RO
sel
RO 0x0
0x0 RO
0x1
USB 2.0 OTG Controller
cv_5v4
2016.10.28
Access Reset
RW 0x0
17 16
Reserved
1 0
toutcal
RW 0x0
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