Altera cyclone V Technical Reference page 2172

Hard processor system
Hide thumbs Also See for cyclone V:
Table of Contents

Advertisement

18-82
gpvndctl
gnptxsts Fields
Bit
30:24
nptxqtop
23:16
nptxqspcavail
15:0
nptxfspcavail
gpvndctl
The application can use this register to access PHY registers. for a ULPI PHY, the core uses the ULPI
interface for PHY register access. The application sets Vendor Control register for PHY register access and
times the PHY register access. The application polls the VStatus Done bit in this register for the
completion of the PHY register access
Altera Corporation
Name
Entry in the Non-periodic Tx Request Queue that is
currently being processed by the MAC. -Bits [30:27]:
Channel/endpoint number -Bits [26:25]: -Bit [24]:
Terminate (last Entry for selected channel endpoint)
Value
0x0
0x1
0x2
0x3
Indicates the amount of free space available in the
Non-periodic Transmit Request Queue. This queue
holds both IN and OUT requests in Host mode.
Device mode has only IN requests. -Others: Reserved
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
Indicates the amount of free space available in the
Non-periodic TxFIFO.Values are in terms of 32-bit
words. 16h0: Non-periodic TxFIFO is full 16h1: 1
word available 16h2: 2 words available 16hn: n words
available (where 0 n 32,768) 16h8000: 32,768 words
available Others: Reserved
Description
Description
IN/OUT token
Zero-length transmit packet (device IN/host
OUT)
PING/CSPLIT token
Channel halt command
Description
Non-periodic Transmit Request Queue is full
1 location available
2 locations available
3 locations available
4 locations available
5 locations available
6 locations available
7 locations available
8 locations available
cv_5v4
2016.10.28
Access
Reset
RO
0x0
RO
0x8
RO
0x400
USB 2.0 OTG Controller
Send Feedback

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents