Altera cyclone V Technical Reference page 2471

cv_5v4
2016.10.28
Bit
1:0
devspd
dctl
Module Instance
usb0
usb1
Offset:
0x804
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
ignrfrmn gmc
um
RW 0x0
RW 0x0
USB 2.0 OTG Controller
Send Feedback
Name
Indicates the speed at which the application requires
the core to enumerate, or the maximum speed the
application can support. However, the actual bus
speed is determined only after the chirp sequence is
completed, and is based on the speed of the USB host
to which the core is connected.
Value
0x0
0x1
0x2
0x3
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reser pwron cgout
ved prgdo nak
ne
WO
RW 0x0
0x0
Description
Description
High speed USB 2.0 PHY clock is 30 MHz or
60 MHz
Full speed USB 2.0 PHY clock is 30 MHz or
60 MHz
Low speed USB 1.1 transceiver clock is 6
MHz
Full speed USB 1.1 transceiver clock is 48
MHz
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
sgout CGNPI sgnpi
nak nNak nnak
WO WO WO
0x0 0x0 0x0
Register Address
0xFFB00804
0xFFB40804
21 20 19 18
5 4 3 2
tstctl goutn gnpin
aksts nakst
RW 0x0
s
RO
0x0 RO
0x0
18-381
dctl
Access Reset
RW 0x0
17 16
nakonbbl
e
RW 0x0
1 0
sftdi rmtwkups
scon ig
RW RW 0x0
0x0
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