Altera cyclone V Technical Reference page 2137

Hard processor system

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gotgint Fields

USB 2.0 OTG Controller

Send Feedback

Mode: Host only. The core sets this bit when the

debounce is completed after the device connect. The

application can start driving USB reset after seeing

this interrupt. This bit is only valid when the HNP

Capable or SRP Capable bit is SET in the Core USB

Configuration register (GUSBCFG.HNPCap or

GUSBCFG.SRPCap, respectively). This bit can be set

only by the core and the application should write 1 to

Mode:Host and Device. The core sets this bit to

indicate that the A-device has timed out WHILE

waiting FOR the B-device to connect. This bit can be

set only by the core and the application should write 1

to clear it.

Mode:Host and Device. The core sets this bit when it

detects a host negotiation request on the USB. This bit

can be set only by the core and the application should

write 1 to clear it.

Debounce completed

A-Device Timeout

Host Negotiation Detected

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