Altera cyclone V Technical Reference page 2494

18-404
dvbuspulse
31 30
15 14
dvbusdis Fields
Bit
15:0
dvbusdis
dvbuspulse
This register specifies the VBUS pulsing time during SRP.
Module Instance
usb0
usb1
Offset:
0x82C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
Altera Corporation
29 28 27 26
13 12 11 10
Name
This value equals: VBUS discharge time in PHY
clocks/​1,024 The value you use depends whether the
PHY is operating at 30 MHz (16-bit data width) or 60
MHz (8-bit data width). Depending on your VBUS
load, this value can need adjustment.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
dvbusdis
RW 0x17D7
Description
Base Address
0xFFB00000
0xFFB40000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
dvbuspulse
21 20 19
5 4 3
Register Address
0xFFB0082C
0xFFB4082C
21 20 19
5 4 3
RW 0x5B8
cv_5v4
2016.10.28
18 17 16
2 1 0
Access Reset
RW 0x17D7
18 17 16
2 1 0
USB 2.0 OTG Controller
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