Altera cyclone V Technical Reference page 2461

cv_5v4
2016.10.28
doeptsiz0
on page 18-640
The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using
Endpoint Enable bit of the Device Control Endpoint 0 Control registers (DIEPCTL0.EPEna/
DOEPCTL0.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 1 to 15. When
Scatter/Gather DMA mode is enabled, this register must not be programmed by the application. If the
application reads this register when Scatter/Gather DMA mode is enabled, the core returns all zeros.
doepdma0
DMA Addressing.
doepdmab0
DMA Buffer Address.
doepctl1 on page 18-643
Out Endpoint 1.
doepint1
on page 18-648
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
doeptsiz1 on page 18-652
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
doepdma1
DMA Addressing.
doepdmab1
DMA Buffer Address.
DOEPCTL2
Out Endpoint 2.
doepint2
on page 18-661
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
doeptsiz2 on page 18-665
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
USB 2.0 OTG Controller
Send Feedback
on page 18-642
on page 18-642
on page 18-654
on page 18-654
on page 18-655
Device Mode Registers Register Descriptions
18-371
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