Altera cyclone V Technical Reference page 2174

Hard processor system

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The application can use this register for general purpose input/output ports or for debugging.

Module Instance

Altera Corporation

The core sets this bit when the vendor control access

is in progress and clears this bit when done.

The application sets this bit for a new vendor

controlaccess.

Set this bit for register writes, and clear it for register

The 6-bit PHY register address for immediate PHY

UTMI+ Vendor Control Register Address (VCtrl):

The 4-bit register address a vendor defined 4-bit

parallel output bus. Bits 11:8 of this field are placed on

utmi_vcontrol[3:0].

ULPI Extended Register Address (ExtRegAddr): The

6-bit PHY extended register address.

Contains the write data for register write. Read data

for register read, valid when VStatus Done is Set.

VStatus Busy inactive

VStatus Busy active

New Register Request not active

New Register Request active

Base Address

USB 2.0 OTG Controller

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