Altera cyclone V Technical Reference page 2144

18-54
gusbcfg
Bit
24
indicator
23
complement
22
termseldlpulse
21
ulpiextvbusindicator
20
ulpiextvbusdrv
Altera Corporation
Name
Mode:Host only. Controls wether the Complement
Output is qualified with the Internal Vbus Valid
comparator before being used in the Vbus State in the
RX CMD.
Value
0x0
0x1
Mode:Host only. Controls the PHY to invert the
ExternalVbusIndicator inputsignal, generating the
ComplementOutput. Please refer to the ULPI Spec for
more detail.
Value
0x0
0x1
Mode:Device only. This bit selects utmi_termselect to
drive data line pulse during SRP.
Value
0x0
0x1
Mode:Host only. This bit indicates to the ULPI PHY to
use an external VBUS overcurrent indicator.
Value
0x0
0x1
Mode:Host only. This bit selects between internal or
external supply to drive 5V on VBUS, in ULPI PHY.
Value
0x0
0x1
Description
Description
Complement Output signal is qualified with the
Internal VbusValid comparator
Complement Output signal is not qualified
with the Internal VbusValid comparator
Description
PHY does not invert ExternalVbusIndicator
signal
PHY does invert ExternalVbusIndicator signal
Description
Data line pulsing using utmi_txvalid
Data line pulsing using utmi_termsel
Description
PHY uses internal VBUS valid comparator
PHY uses external VBUS valid comparator
Description
PHY drives VBUS using internal charge pump
PHY drives VBUS using external supply
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
USB 2.0 OTG Controller
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