Altera cyclone V Technical Reference page 2188

18-98
ghwcfg4
Bit
19:16
numctleps
15:14
phydatawidth
6
hibernation
5
ahbfreq
Altera Corporation
Name
Specifies the number of Device mode control
endpoints in addition to control endpoint 0, which is
always present. Range: 0-15.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
Uses a ULPI interface only. Hence only 8-bit setting is
relevant. This setting should not matter since UTMI is
not enabled.
Enables power saving mode hibernation.
Value
0x0
When the AHB frequency is less than 60 MHz, 4-
deep clock-domain crossing sink and source buffers
are instantiated between the MAC and the Packet
FIFO Controller (PFC); otherwise, two-deep buffers
are sufficient.
Value
0x1
Description
Description
End point 0
End point 1
End point 2
End point 3
End point 4
End point 5
End point 6
End point 7
End point 8
End point 9
End point 10
End point 11
End point 12
End point 13
End point 14
End point 15
Description
Hibernation feature disabled
Description
Minimum AHB Frequency Less Than 60 MH
cv_5v4
2016.10.28
Access Reset
RO 0xF
RO 0x0
RO 0x0
RO 0x1
USB 2.0 OTG Controller
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