Altera cyclone V Technical Reference page 2307

Hard processor system
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cv_5v4
2016.10.28
31
30
15
14
Reserved
frm_
lst_
rolli
ntrms
0x0
hcintmsk5 Fields
Bit
13
frm_lst_rollintrmsk
11
bnaintrmsk
2
ahberrmsk
1
chhltdmsk
USB 2.0 OTG Controller
Send Feedback
29
28
27
26
13
12
11
10
Reser
bnain
ved
trmsk
RW
0x0
k
RW
Name
This bit is valid only when Scatter/Gather DMA mode
is enabled.
0x0
0x1
This bit is valid only when Scatter/Gather DMA mode
is enabled.
0x0
0x1
In scatter/gather DMA mode for host, interrupts will
not be generated due to the corresponding bits set in
HCINTn.
0x0
0x1
Channel Halted.
0x0
0x1
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Reserved
Description
Value
Description
Mask
No mask
Value
Description
Mask
No mask
Value
Description
Mask
No mask
Value
Description
Mask
No mask
hcintmsk5
21
20
19
18
5
4
3
2
ahber
rmsk
RW
0x0
Access
RW
RW
RW
RW
18-217
17
16
1
0
chhlt
xfercomp
dmsk
lmsk
RW
RW 0x0
0x0
Reset
0x0
0x0
0x0
0x0
Altera Corporation

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