Altera cyclone V Technical Reference page 2400

18-310
hcint12
Bit
15:14
xactpos
13:7
hubaddr
6:0
prtaddr
hcint12
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All
Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt
register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
HAINT and GINTSTS registers.
Module Instance
usb0
usb1
Offset:
0x688
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
Name
This field is used to determine whether to send all,
first, middle, or last payloads with each OUT transac‐
tion.
Value
0x0
0x1
0x2
0x3
This field holds the device address of the transaction
translator's hub.
This field is the port number of the recipient transac‐
tiontranslator.
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
Mid. This is the middle payload of this
transaction (which is larger than 188 bytes)
End. This is the last payload of this transac‐
tion (which is larger than 188 bytes)
Begin. This is the first data payload of this
transaction (which is larger than 188 bytes)
All. This is the entire data payload is of this
transaction (which is less than or equal to 188
bytes)
Base Address
Access
Register Address
0xFFB00688
0xFFB40688
USB 2.0 OTG Controller
cv_5v4
2016.10.28
Reset
RW 0x0
RW 0x0
RW 0x0
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