Altera cyclone V Technical Reference page 2113
Hard processor system
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Also See for cyclone V:
- Device handbook (1077 pages) ,
- User manual (136 pages) ,
- Reference manual (66 pages)
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cv_5v4
2016.10.28
Register
hcintmsk8
on page 18-
258
hctsiz8
on page 18-
260
hcdma8
on page 18-261
hcdmab8
on page 18-
263
hcchar9
on page 18-
263
hcsplt9
on page 18-
266
hcint9
on page 18-268
hcintmsk9
on page 18-
272
hctsiz9
on page 18-
274
hcdma9
on page 18-275
hcdmab9
on page 18-
277
hcchar10
on page 18-
277
hcsplt10
on page 18-
280
hcint10
on page 18-
282
hcintmsk10
on page
18-286
hctsiz10
on page 18-
288
hcdma10
on page 18-
289
hcdmab10
on page 18-
291
hcchar11
on page 18-
291
HCSPLT11
on page 18-
294
USB 2.0 OTG Controller
Send Feedback
USB OTG Controller Module Registers Address Map
Offset
Width Acces
s
0x60C
32
RW
0x610
32
RW
0x614
32
RW
0x618
32
RW
0x620
32
RW
0x624
32
RW
0x628
32
RO
0x62C
32
RW
0x630
32
RW
0x634
32
RW
0x638
32
RW
0x640
32
RW
0x644
32
RW
0x648
32
RO
0x64C
32
RW
0x650
32
RW
0x654
32
RW
0x658
32
RW
0x660
32
RW
0x664
32
RW
Reset Value
Host Channel 8 Interrupt Mask
0x0
Register
Host Channel 8 Transfer Size
0x0
Register
Host Channel 8 DMA Address
0x0
Register
Host Channel 8 DMA Buffer
0x0
Address Register
Host Channel 9 Characteristics
0x0
Register
Host Channel 9 Split Control
0x0
Register
Host Channel 9 Interrupt Register
0x0
Host Channel 9 Interrupt Mask
0x0
Register
Host Channel 9 Transfer Size
0x0
Register
Host Channel DMA Address
0x0
Register
Host Channel 9 DMA Buffer
0x0
Address Register
Host Channel 10 Characteristics
0x0
Register
Host Channel 10 Split Control
0x0
Register
Host Channel 10 Interrupt
0x0
Register
Host Channel 10 Interrupt Mask
0x0
Register
Host Channel 10 Transfer Size
0x0
Register
Host Channel 10 DMA Address
0x0
Register
Host Channel 10 DMA Buffer
0x0
Address Register
Host Channel 11 Characteristics
0x0
Register
Host Channel 11 Split Control
0x0
Register
18-23
Description
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