Altera cyclone V Technical Reference page 2456

18-366
Device Mode Registers Register Descriptions
dieptsiz6
on page 18-503
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
diepdma6
DMA Addressing.
dtxfsts6
on page 18-505
This register contains the free space information for the Device IN endpoint TxFIFO.
diepdmab6
DMA Buffer Address.
diepctl7
on page 18-507
Endpoint_number: 7
diepint7
on page 18-513
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
dieptsiz7
on page 18-517
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
diepdma7
DMA Addressing.
dtxfsts7
on page 18-519
This register contains the free space information for the Device IN endpoint TxFIFO.
diepdmab7
DMA Buffer Address.
diepctl8 on page 18-521
Endpoint_number: 8
diepint8
on page 18-527
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
Altera Corporation
on page 18-504
on page 18-506
on page 18-518
on page 18-520
cv_5v4
2016.10.28
USB 2.0 OTG Controller
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