Altera cyclone V Technical Reference page 2451

cv_5v4
2016.10.28
hcdmab15
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
Module Instance
usb0
usb1
Offset:
0x6F8
Access:
RW
31 30
15 14
hcdmab15 Fields
Bit
31:0
hcdmab15
Device Mode Registers Register Descriptions
These registers must be programmed every time the USB OTG Controller changes to Device mode.
Offset:
0x800
dcfg on page 18-377
This register configures the core in Device mode after power-on or after certain control commands or
enumeration. Do not make changes to this register after initial programming.
dctl
on page 18-381
USB 2.0 OTG Controller
Send Feedback
0xFFB00000
0xFFB40000
29 28 27 26
13 12 11 10
Name
These registers are present only in case of Scatter/
Gather DMA. These registers are implemented in
RAM instead of flop-based implementation. Holds
the current buffer address. This register is updated as
and when the data transfer for the corresponding end
point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is
reserved.
Base Address
Bit Fields
25 24 23 22
hcdmab15
RW 0x0
9 8 7 6
hcdmab15
RW 0x0
Description
hcdmab15
Register Address
0xFFB006F8
0xFFB406F8
21 20 19 18
5 4 3 2
Access
18-361
17 16
1 0
Reset
RW 0x0
Altera Corporation