Altera cyclone V Technical Reference page 2227

Hard processor system

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prtovrcurrchng

prtovrcurract

USB 2.0 OTG Controller

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The core sets this bit when the status of the PortOver‐

current Active bit (bit 4) in this register changes.This

bit can be set only by the core and the application

should write 1 to clear it

Indicates the overcurrent condition of the port. 0x0:

No overcurrent condition 0x1: Overcurrent condition

The core sets this bit when the status of the Port

Enable bit [2] of this register changes. This bit can be

set only by the core and the application should write 1

to clear it.

A port is enabled only by the core after a reset

sequence, and is disabled by an overcurrent

condition, a disconnect condition, or by the applica‐

tion clearing this bit. The application cannot Set this

bit by a register write. It can only clear it to disable the

port by writing 1. This bit does not trigger any

interrupt to the application.

Status of port overcurrent no change

Status of port overcurrent changed

No overcurrent condition

Overcurrent condition

Port Enable bit 2 no change

Port Enable bit 2 changed

Port disabled

Port enabled

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