Altera cyclone V Technical Reference page 2145

Hard processor system

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USB 2.0 OTG Controller

Send Feedback

Mode:Host and Device. This bit sets the ClockSus‐

pendM bit in the Interface Control register on the ULPI

PHY. This bit applies only in serial or carkit modes.

PHY powers down internal clock during

PHY does not power down internal clock

Mode:Host and Device. This bit sets the AutoResume

bit in the Interface Control register on the ULPI PHY.

PHY does not use AutoResume feature

PHY uses AutoResume feature

Mode: Device only. Sets the turnaround time in PHY

clocks. Specifies the response time for a MAC request to

the Packet FIFO Controller (PFC) to fetch data from

the DFIFO (SPRAM). The value is calculated for the

minimum AHB frequency of 30 MHz. USB turnaround

time is critical for certification where long cables and 5-

Hubs are used, so If you need the AHB to run at less

than 30 MHz, and If USB turnaround time is not

critical, these bits can be programmed to a larger value.

MAC interface is 8-bit UTMI+.

Mode:Host and Device. The application uses this bit to

control the otg core's HNP capabilities.

HNP capability is not enabled.

HNP capability is enabled

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