Altera cyclone V Technical Reference page 2158

Hard processor system

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Mode: Device only. This interrupt is valid only in

shared FIFO operation. Indicates that an IN token has

been received for a non-periodic endpoint, but the

data for another endpoint is present in the top of the

Non-periodic Transmit FIFO and the IN endpoint

mismatch count programmed by the application has

Mode: Device only. The core sets this bit when it fails

to write an isochronous OUT packet into the RxFIFO

because the RxFIFO does not have enough space to

accommodate a maximum packet size packet for the

isochronous OUT endpoint.

Mode: Device only. The core sets this bit to indicate

that speed enumeration is complete. The application

must read the Device Status register to obtain the

enumerated speed.

Mode: Device only. The core sets this bit to indicate

that a reset is detected on the USB.

Endpoint Mismatch Interrup

Isochronous OUT Packet Dropped Interrup

Enumeration Done

USB 2.0 OTG Controller

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