Altera cyclone V Technical Reference page 2213

cv_5v4
2016.10.28
hcdma15
on page 18-359
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for
IN/OUT transactions. The starting DMA address must be DWORD-aligned.
hcdmab15
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
hcfg
Host Mode control. This register must be programmed every time the core changes to Host mode
Module Instance
usb0
usb1
Offset:
0x400
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
modechti
men
RW 0x0
15 14
USB 2.0 OTG Controller
Send Feedback
on page 18-361
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved persc
heden
a
RW
0x0
13 12 11 10
resvalid
RW 0x2
Base Address
Bit Fields
25 24 23 22
frlisten descd
ma
RW 0x0
RW
0x0
9 8 7 6
ena32
khzs
RW
0x0
Register Address
0xFFB00400
0xFFB40400
21 20 19 18
Reserved
5 4 3 2
Reserved fslss
upp
RW
0x0
18-123
hcfg
17 16
1 0
fslspclksel
RW 0x0
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