Altera cyclone V Technical Reference page 2216

Hard processor system

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This register stores the frame interval information for the current speed to which the otg core has

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

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When the core is in FS Host mode. The internal PHY

clock is running at 30/60 MHZ for ULPI PHY

Interfaces. The internal PHY clock is running at

48MHZ for 1.1 FS transceiver Interface When the

core is in LS Host mode, the internal PHY clock is

running at 30/60 MHZ for ULPI PHY Interfaces. The

internal PHY clock is running at 6 MHZ and the

external clock is running at 48MHZ. When you select

a 6 MHz clock during LS Mode, you must do a soft

reset for 1.1 FS transceiver Interface. * When Core in

FS mode, the internal and external clocks have the

same frequency. * When Core in LS mode, - If

fslspclksel is 30/60 Mhz internal and external clocks

have the same frequency. - If fslspclksel is 6Mhz the

internal clock is divided by eight of external 48 MHz

clock (utmifs_clk).

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

PHY clock is running at 30/60 MHz

PHY clock is running at 48 MHz

PHY clock is running at 6 MHz

Base Address

USB 2.0 OTG Controller

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