Altera cyclone V Technical Reference page 2146

18-56
gusbcfg
Bit
8
srpcap
7
ddrsel
6
physel
5
fsintf
4
ulpi_utmi_sel
Altera Corporation
Name
Mode:Host and Device. The application uses this bit to
control the otg core SRP capabilities. If the core
operates as a non-SRP-capable B-device, it cannot
request the connected A-device (host) to activate VBUS
and start a session. This bit is writable only If an SRP
mode was specified for Mode of Operation in coreCon‐
sultant (parameter OTG_MODE). Otherwise, reads
Return 0.
Value
0x0
0x1
Mode:Host and Device. The application uses this bit to
select a Single Data Rate (SDR) ULPI interface. DDR is
not supported.
Value
0x0
0x1
Mode:Host and Device. The application uses USB 2.0.
Value
0x0
Mode:Host and Device. The application can Set this bit
to select between the 3- and 6-pin interfaces, and access
is Read and Write.
Value
0x0
0x1
Mode:Host and Device. The application uses ULPI
Only in 8bit mode.
0x0
0x1
Description
Description
SRP capability is not enabled
SRP capability is enabled
Description
Single Data Rate ULPI Interfacewith 8-bit-wide
data bus
Reserved
Description
USB 2.0 high-speed ULPI
Description
6-pin unidirectional full-speed serial interface
3-pin bidirectional full-speed serial interface
Value
ULPI PHY
UTMI PHY
Description
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RO 0x0
RO 0x0
RO 0x1
USB 2.0 OTG Controller
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