Altera cyclone V Technical Reference page 2462

18-372
Device Mode Registers Register Descriptions
doepdma2
DMA Addressing.
doepdmab2
DMA Buffer Address.
DOEPCTL3
Out Endpoint 3.
doepint3
on page 18-674
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
doeptsiz3
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
doepdma3
DMA OUT Address.
doepdmab3
DMA Buffer Address.
doepctl4 on page 18-681
Out Endpoint 4.
Doepint4
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
doeptsiz4
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/
DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the
core has cleared the Endpoint Enable bit.
doepdma4
DMA OUT Address.
doepdmab4
DMA Buffer Address.
doepctl5
on page 18-694
Out Endpoint 5.
Altera Corporation
on page 18-667
on page 18-667
on page 18-668
on page 18-678
on page 18-680
on page 18-680
on page 18-687
on page 18-691
on page 18-693
on page 18-693
cv_5v4
2016.10.28
USB 2.0 OTG Controller
Send Feedback