Altera cyclone V Technical Reference page 2409

cv_5v4
2016.10.28
hcdmab12
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
Module Instance
usb0
usb1
Offset:
0x698
Access:
RW
31 30
15 14
hcdmab12 Fields
Bit
31:0
hcdmab12
hcchar13
Host Channel 13 Characteristics Register
Module Instance
usb0
usb1
USB 2.0 OTG Controller
Send Feedback
0xFFB00000
0xFFB40000
29 28 27 26
13 12 11 10
Name
These registers are present only in case of Scatter/
Gather DMA. These registers are implemented in
RAM instead of flop-based implementation. Holds
the current buffer address. This register is updated as
and when the data transfer for the corresponding end
point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is
reserved.
0xFFB00000
0xFFB40000
Base Address
Bit Fields
25 24 23 22
hcdmab12
RW 0x0
9 8 7 6
hcdmab12
RW 0x0
Description
Base Address
hcdmab12
Register Address
0xFFB00698
0xFFB40698
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB006A0
0xFFB406A0
18-319
17 16
1 0
Reset
RW 0x0
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