Altera cyclone V Technical Reference page 2480

18-390
doepmsk
Bit
3
timeoutmsk
2
ahberrmsk
1
epdisbldmsk
0
xfercomplmsk
doepmsk
This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers for all
endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in
the DOEPINTn register can be masked by writing into the corresponding bit in this register. Status bits are
masked by default
Module Instance
usb0
usb1
Offset:
0x814
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
Name
Non-isochronous endpoints
Value
0x0
0x1
Value
0x0
0x1
Value
0x0
0x1
Value
0x0
0x1
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
Mask Timeout Condition Interrupt
No Mask Timeout Condition Interrupt
Description
Mask AHB Error Interrupt
No Mask AHB Error Interrupt
Description
Mask Endpoint Disabled Interrupt
No Mask Endpoint Disabled Interrupt
Description
Mask Transfer Completed Interrupt
No Mask Transfer Completed Interrupt
Base Address
Access
Register Address
0xFFB00814
0xFFB40814
USB 2.0 OTG Controller
cv_5v4
2016.10.28
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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