Altera cyclone V Technical Reference page 2222

18-132
haintmsk
31 30
15 14
haint Fields
Bit
15:0
haint
haintmsk
The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to
interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel,
up to a maximum of 16 bits.
Module Instance
usb0
usb1
Offset:
0x418
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
29 28 27 26
13 12 11 10
Name
One bit per channel: Bit 0 for Channel 0, bit 15 for
Channel 15
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
haint
RO 0x0
Description
Base Address
0xFFB00000
0xFFB40000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
haintmsk
RW 0x0
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB00418
0xFFB40418
21 20 19 18
5 4 3 2
USB 2.0 OTG Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RO 0x0
17 16
1 0
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