Altera cyclone V Technical Reference page 2477

Hard processor system

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USB 2.0 OTG Controller

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When the core is operating at high speed, this field

contains a microframe number. When the core is

operating at full or low speed, this field contains a

Frame number.

The core sets this bit to report any erratic errors (phy_

rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted

for at least 2 ms, due to PHY error) seen on the UTMI

+ . Due to erratic errors, the otg core goes into

Suspended state and an interrupt is generated to the

application with Early Suspend bit of the Core

Interrupt register (GINTSTS.ErlySusp). If the early

suspend is asserted due to an erratic error, the

application can only perform a soft disconnect

Indicates the speed at which the otg core has come up

after speed detection through a chirp sequence.

No Erratic Error

Erratic Error

High speed (PHY clock is running at 30 or 60

Full speed (PHY clock is running at 30 or 60

Low speed (PHY clock is running at 6 MHz)

Full speed (PHY clock is running at 48 MHz)

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