Altera cyclone V Technical Reference page 2217

Hard processor system

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This register contains the free space information for the Periodic TxFIFO and the Periodic Transmit

Request Queue

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This bit allows dynamic reloading of the HFIR

reloaded dynamically0x1: the HFIR can be

dynamically reloaded during runtime. This bit needs

to be programmed during initial configuration and its

value should not be changed during runtime.

The value that the application programs to this field

specifies the interval between two consecutive SOFs

(FS) or micro- SOFs (HS) or Keep-Alive tokens (HS).

This field contains the number of PHY clocks that

constitute the required frame interval. The Default

value Set in this field for a FS operation when the

PHY clock frequency is 60 MHz. The application can

write a value to this register only after the Port Enable

bit of the Host Port Control and Status register

(HPRT.PrtEnaPort) has been Set. If no value is

programmed, the core calculates the value based on

the PHY clock specified in the FS/LS PHY Clock

Select field of the Host Configuration register

(HCFG.FSLSPclkSel). Do not change the value of this

field after the initial configuration. 125 s * (PHY clock

frequency for HS) 1 ms * (PHY clock frequency for

The HFIR cannot be reloaded dynamically

The HFIR can be dynamically reloaded

during runtime

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