Altera cyclone V Technical Reference page 2215

cv_5v4
2016.10.28
Bit
23
descdma
15:8
resvalid
7
ena32khzs
2
fslssupp
USB 2.0 OTG Controller
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Name
The application can set this bit during initialization to
enable the Scatter/Gather DMA operation. This bit
must be modified only once after a reset. The
following combinations are available for program‐
ming: GAHBCFG.DMAEn=0,HCFG.DescDMA=0
=> Slave mode
GAHBCFG.DMAEn=0,HCFG.DescDMA=1 =>
InvalidGAHBCFG.DMAEn=1,HCFG.DescDMA=0
=> Buffered DMA mode
GAHBCFG.DMAEn=1,HCFG.DescDMA=1 =>
Scatter/Gather DMA mode
Value
0x0
0x1
This field is effective only when HCFG.Ena32KHzS is
set. It will control the resume period when the core
resumes from suspend. The core counts for ResValid
number of clock cycles to detect a valid resume when
this is set.
This bit can only be set if the USB 1.1 Full-Speed
Serial Transceiver Interface has been selected. If USB
1.1 Full-Speed Serial Transceiver Interface has not
been selected, this bit must be zero. When the USB
1.1 Full-Speed Serial Transceiver Interface is chosen
and this bit is set, the core expects the 48-MHz PHY
clock to be switched to 32 KHz during a suspend.
Value
0x0
0x1
The application uses this bit to control the core's
enumeration speed. Using this bit, the application can
make the core enumerate as a FS host, even If the
connected device supports HS traffic. Do not make
changes to this field after initial programming.
Value
0x0
0x1
Description
Description
No Scatter/Gather DMA
Scatter/Gather DMA selected
Description
USB 1.1 Full-Speed Not Selected
USB 1.1 Full-Speed Serial Transceiver
Interface selected
Description
HS/FS/LS, based on the maximum speed
supported by the connected device
FS/LS-only, even if the connected device can
support HS
18-125
hcfg
Access Reset
RW 0x0
RW 0x2
RW 0x0
RW 0x0
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