Altera cyclone V Technical Reference page 2214

Hard processor system

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This bit is used to enable or disable the host core to

wait for 200 PHY clock cycles at the end of Resume to

change the opmode signal to the PHY to 00 after

Suspend or LPM.

Applicable in Scatter/Gather DMA mode only.

Enables periodic scheduling within the core. Initially,

the bit is reset. The core will not process any periodic

channels. As soon as this bit is set, the core will get

ready to start scheduling periodic channels. In non

Scatter/Gather DMA mode, this bit is reserved.

The value in the register specifies the number of

entries in the Frame list. This field is valid only in

Scatter/Gather DMA mode.

The Host core waits for either 200 PHY clock

cycles or a linestate of SE0 at the end of

resume to change the opmode from 0x2 to

The Host core waits only for a linestate of SE0

at the end of resume to change the opmode

from 0x2 to 0x0

Disables periodic scheduling within the core

Enables periodic scheduling within the core

USB 2.0 OTG Controller

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