Altera cyclone V Technical Reference page 2168

Hard processor system

Hide thumbs Also See for cyclone V:

Table of Contents

A read to the Receive Status Read and Pop register additionally pops the: top data entry out of the RxFIFO.

The receive status contents must be interpreted differently in Host and Device modes. The core ignores the

receive status pop/read when the receive FIFO is empty and returns a value of 0. The application must only

pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register

(GINTSTS.RxFLvl) is asserted. Use of these fields vary based on whether the HS OTG core is functioning

as a host or a device. Do not read this register'ss reset value before configuring the core because the read

value is "X" in the simulation.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

grxstsp Fields

Altera Corporation

Indicates the endpoint number to which the current

received packet belongs.

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

Mode: Device only. This is the least significant 4 bits

of the (micro)Frame number in which the packet is

received on the USB. This field is supported only

when isochronous OUT endpoints are supported.

Base Address

USB 2.0 OTG Controller

Send Feedback

Show Quick Links

Table of Contents