Altera cyclone V Technical Reference page 2128

18-38
Global Registers Register Descriptions
grxstsr
on page 18-76
A read to the Receive Status Read and Pop register additionally pops the: top data entry out of the RxFIFO.
The receive status contents must be interpreted differently in Host and Device modes. The core ignores the
receive status pop/read when the receive FIFO is empty and returns a value of 0. The application must only
pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register
(GINTSTS.RxFLvl) is asserted. Use of these fields vary based on whether the HS OTG core is functioning
as a host or a device. Do not read this register's reset value before configuring the core because the read
value is "X" in the simulation.
grxstsp
on page 18-78
A read to the Receive Status Read and Pop register additionally pops the: top data entry out of the RxFIFO.
The receive status contents must be interpreted differently in Host and Device modes. The core ignores the
receive status pop/read when the receive FIFO is empty and returns a value of 0. The application must only
pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register
(GINTSTS.RxFLvl) is asserted. Use of these fields vary based on whether the HS OTG core is functioning
as a host or a device. Do not read this register'ss reset value before configuring the core because the read
value is "X" in the simulation.
grxfsiz on page 18-79
The application can program the RAM size that must be allocated to the RxFIFO.
gnptxfsiz
The application can program the RAM size and the memory start address for the Non-periodic TxFIFO.
The fields of this register change, depending on host or device mode.
gnptxsts
on page 18-81
In Device mode, this register is valid only in Shared FIFO operation. It contains the free space information
for the Non-periodic TxFIFO and the Nonperiodic Transmit RequestQueue
gpvndctl
on page 18-82
The application can use this register to access PHY registers. for a ULPI PHY, the core uses the ULPI
interface for PHY register access. The application sets Vendor Control register for PHY register access and
times the PHY register access. The application polls the VStatus Done bit in this register for the
completion of the PHY register access
ggpio on page 18-84
The application can use this register for general purpose input/output ports or for debugging.
guid
on page 18-85
This is a read/write register containing the User ID. This register can be used in the following ways: -To
store the version or revision of your system -To store hardware configurations that are outside the otg core
As a scratch register
gsnpsid
on page 18-86
This read-only register contains the release number of the core being used.
ghwcfg1
on page 18-87
This register contains the logical endpoint direction(s).
ghwcfg2 on page 18-87
This register contains configuration options.
ghwcfg3
on page 18-92
This register contains the configuration options.
Altera Corporation
on page 18-80
cv_5v4
2016.10.28
USB 2.0 OTG Controller
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