Altera cyclone V Technical Reference page 2556

Hard processor system
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18-466
diepctl4
diepctl4 Fields
Bit
31
epena
30
epdis
Altera Corporation
Name
Applies to IN and OUT endpoints. -When Scatter/
Gather DMA mode is enabled, -for IN endpoints this
bit indicates that the descriptor structure and data
buffer with data ready to transmit is setup. -for OUT
endpoint it indicates that the descriptor structure and
data buffer to receive data is setup. -When Scatter/
Gather DMA mode is enabled such as for buffer-
pointer based DMA mode: - for IN endpoints, this bit
indicates that data is ready to be transmitted on the
endpoint. - for OUT endpoints, this bit indicates that
the application has allocated the memory to start
receiving data from the USB. - The core clears this bit
before setting any of the following interrupts on this
endpoint: -SETUP Phase Done -Endpoint Disabled -
Transfer Completed for control endpoints in DMA
mode, this bit must be set to be able to transfer
SETUP data packets in memory.
Value
0x0
0x1
Applies to IN and OUT endpoints. The application
sets this bit to stop transmitting/receiving data on an
endpoint, even before the transfer for that endpoint is
complete. The application must wait for the Endpoint
Disabled interrupt before treating the endpoint as
disabled. The core clears this bit before setting the
Endpoint Disabled interrupt. The application must set
this bit only if Endpoint Enable is already set for this
endpoint.
Value
0x0
0x1
Description
Description
Endpoint Enable inactive
Endpoint Enable active
Description
No Endpoint Disable
Endpoint Disable
cv_5v4
2016.10.28
Access
Reset
RO
0x0
RO
0x0
USB 2.0 OTG Controller
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