Altera cyclone V Technical Reference page 2150

Hard processor system

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Mode:Host and Device. The application can flush the

entire RxFIFO using this bit, but must first ensure

that the core is not in the middle of a transaction. The

application must only write to this bit after checking

that the core is neither reading from the RxFIFO nor

writing to the RxFIFO. The application must wait

until the bit is cleared before performing any other

operations. This bit requires 8 clocks (slowest of PHY

or AHB clock) to clear.

Mode:Host only. The application writes this bit to

reset the (micro)frame number counter inside the

core. When the (micro)frame counter is reset, the

subsequent SOF sent out by the core has a (micro)

frame number of 0. When application writes 1 to the

bit, it might not be able to read back the value as it

will get cleared by the core in a few clock cycles.

no flush the entire RxFIFO

flush the entire RxFIFO

Host Frame Counter Reset

USB 2.0 OTG Controller

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