Altera cyclone V Technical Reference page 2506

Hard processor system

Hide thumbs Also See for cyclone V:

Table of Contents

Altera Corporation

This bit indicates to the application that an ISOC

OUT packet has been dropped. This bit does not have

an associated mask bit and does not generate an

This bit is valid only when Scatter/Gather DMA mode

is enabled. The core generates this interrupt when the

descriptor accessed is not ready for the Core to

process, such as Host busy or DMA done

Applies to IN endpoints Only. The core generates this

interrupt when it detects a transmit FIFO underrun

condition for this endpoint.

This bit is valid only for IN Endpoints This interrupt

is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or

completely empty status is determined by the TxFIFO

Empty Level bit in the Core AHB Configuration

No interrupt

Packet Drop Status interrupt

No interrupt

BNA interrupt

No interrupt

Fifo Underrun interrupt

No interrupt

Transmit FIFO Empty interrupt

USB 2.0 OTG Controller

Send Feedback

Show Quick Links

Table of Contents