Altera cyclone V Technical Reference page 2483

cv_5v4
2016.10.28
Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). There is one interrupt bit per
endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. for a bidirectional
endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared
when the application sets and clears bits in the corresponding Device Endpoint-n Interrupt register
(DIEPINTn/DOEPINTn).
Module Instance
usb0
usb1
Offset:
0x818
Access:
RO
31 30
outepint outep outep
15 int14 int13
RO 0x0 RO
0x0 0x0
15 14
inepint1 inepi inepi
5 nt14 nt13
RO 0x0 RO
0x0 0x0
daint Fields
Bit
31
outepint15
30
outepint14
USB 2.0 OTG Controller
Send Feedback
0xFFB00000
0xFFB40000
29 28 27 26
outep outep outep
int12 int11 int10
RO RO RO RO
0x0 0x0 0x0
13 12 11 10
inepi inepi inepi
nt12 nt11 nt10
RO RO RO RO
0x0 0x0 0x0
Name
Value
0x0
0x1
Value
0x0
0x1
Base Address
Bit Fields
25 24 23 22
outep outep outep outep
int9 int8 int7 int6
RO RO RO RO
0x0 0x0 0x0 0x0
9 8 7 6
inepi inepi inepi inepi
nt9 nt8 nt7 nt6
RO RO RO RO
0x0 0x0 0x0 0x0
Description
Description
No Interrupt
OUT Endpoint 15 Interrupt
Description
No Interrupt
OUT Endpoint 14 Interrupt
Register Address
0xFFB00818
0xFFB40818
21 20 19 18
outep outep outep outep
int5 int4 int3 int2
RO RO RO RO
0x0 0x0 0x0 0x0
5 4 3 2
inepi inepi inepi inepi
nt5 nt4 nt3 nt2
RO RO RO RO
0x0 0x0 0x0 0x0
Access
18-393
daint
17 16
outep outepint
int1 0
RO RO 0x0
0x0
1 0
inepi inepint0
nt1
RO 0x0
RO
0x0
Reset
RO 0x0
RO 0x0
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