Altera cyclone V Technical Reference page 2541

cv_5v4
2016.10.28
diepdmab2 Fields
Bit
31:0
diepdmab2
diepctl3
Endpoint_number: 3
Module Instance
usb0
usb1
Offset:
0x960
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
epena epdis setd1
pid
RO 0x0 RO
0x0
0x0
15 14
usbactep
RW 0x0
USB 2.0 OTG Controller
Send Feedback
Name
Holds the current buffer address. This register is
updated as and when the data transfer for the
corresponding end point is in progress. This register is
present only in Scatter/Gather DMA mode.
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
setd0 snak cnak
pid
WO WO
WO WO 0x0 0x0
0x0
13 12 11 10
Reserved
Description
Base Address
Bit Fields
25 24 23 22
txfnum
RW 0x0
9 8 7 6
diepctl3
Access
Register Address
0xFFB00960
0xFFB40960
21 20 19 18
stall Reser eptype
ved
RO RW 0x0
0x0
5 4 3 2
mps
RW 0x0
18-451
Reset
RO 0x0
17 16
nakst dpid
s
RO 0x0
RO
0x0
1 0
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