Altera cyclone V Technical Reference page 2211

cv_5v4
2016.10.28
hcchar12
on page 18-305
Host Channel 1 Characteristics Register
hcsplt12 on page 18-308
Channel_number 1
hcint12
on page 18-310
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All
Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt
register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
HAINT and GINTSTS registers.
hcintmsk12
This register reflects the mask for each channel status described in the previous section.
hctsiz12
on page 18-316
Buffer DMA Mode
hcdma12 on page 18-317
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for
IN/OUT transactions. The starting DMA address must be DWORD-aligned.
hcdmab12
These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM
instead of flop-based implementation. Holds the current buffer address. This register is updated as and
when the data transfer for the corresponding end point is in progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this field is reserved.
hcchar13 on page 18-319
Host Channel 13 Characteristics Register
hcsplt13
on page 18-322
Channel_number 13.
hcint13 on page 18-324
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All
Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt
register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
HAINT and GINTSTS registers.
hcintmsk13
This register reflects the mask for each channel status described in the previous section.
hctsiz13 on page 18-330
Buffer DMA Mode
hcdma13
on page 18-331
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for
IN/OUT transactions. The starting DMA address must be DWORD-aligned.
USB 2.0 OTG Controller
Send Feedback
on page 18-314
on page 18-319
on page 18-328
Host Mode Registers Register Descriptions
18-121
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