Altera cyclone V Technical Reference page 2143

Hard processor system

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gusbcfg Fields

corrupttxpkt

forcedevmode

forcehstmode

USB 2.0 OTG Controller

Send Feedback

Mode: Host and device. This bit is for debug purposes

only. Never Set this bit to 1. The application should

always write 0 to this bit.

Mode:Host and device. Writing a 1 to this bit forces the

core to device mode. After setting the force bit, the

application must wait at least 25 ms before the change

to take effect. When the simulation is in scale down

mode, waiting for 500 micro-sec is sufficient.

Force Device Mode

Mode:Host and device. Writing a 1 to this bit forces the

core to host mode After setting the force bit, the

application must wait at least 25 ms before the change

to take effect. When the simulation is in scale down

mode, waiting for 500 micro-sec is sufficient.

Force Host Mode

Mode: Device only. Set to non UTMI+.

Mode:Host only. Controls circuitry built into the PHY

for protecting the ULPI interface when the link tri-

states STP and data. Any pull-ups or pull-downs

employed by this feature can be disabled.

Enables the interface protect circuit

Disables the interface protect circuit

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