Altera cyclone V Technical Reference page 2411

Hard processor system

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USB 2.0 OTG Controller

Send Feedback

When the Split Enable bit of the Host Channel-n Split

Control register (HCSPLTn.SpltEna) is reset (0), this

field indicates to the host the number of transactions

that must be executed per microframe for this

periodic endpoint. for non periodic transfers, this

field is used only in DMA mode, and specifies the

number packets to be fetched for this channel before

the internal DMA engine changes arbitration. When

HCSPLTn.SpltEna is Set (1), this field indicates the

number of immediate retries to be performed for a

periodic split transactions on transaction errors. This

field must be set to at least 1.

Indicates the transfer type selected.

This field is set by the application to indicate that this

channel is communicating to a low-speed device. The

application must program this bit when a low speed

device is connected to the host through an FS HUB.

The HS OTG Host core uses this field to drive the

XCVR_SELECT signal to 0x3 while communicating

to the LS Device through the FS hub. In a peer to peer

setup, the HS OTG Host core ignores this bit even if it

is set by the application software

Reserved This field yields undefined result

1 transaction

2 transactions to be issued for this endpoint

per microframe

3 transactions to be issued for this endpoint

per microframe

Not Communicating with low speed device

Communicating with low speed device

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